1. Field of the Invention
The present invention relates to a communication system, and in particular to a dual apparatus and a method thereof having a PCI bridge having a concurrent write function.
2. Background of the Related Art
In a communication system, an apparatus which may fatally damage the system if it fails is implemented as dual. In general, there are two dual implementations. These are a warm standby dual method and a hot standby dual method.
In the warm standby dual method, an active board is operated and a standby board is not operated. Accordingly, an operation for synchronizing a memory of the active board with a memory of the standby board is required.
In the hot standby dual method, one board is operated as a primary board, and the other board is operated as a secondary board. An output of the primary board is used as an effective output, and an operation for synchronizing memories of the two boards with each other is not required.
Herein, the warm standby dual method will be described.
FIG. 1 is a drawing illustrating a construction of an exemplary dual apparatus using a peripheral component interconnect (PCI) bridge.
As depicted in FIG. 1, the dual apparatus using the PCI bridge includes a first board 10 and a second board 20. The first board 10 and the second board 20 are connected with each other by the PCI bus 30.
The first board 10 includes a first processor 11 for outputting data and a control signal and a first main memory 12 for storing the data according to the control signal. The first board 10 also includes a first PCI bridge 14 for exchanging information with the second board 20 through the PCI bus 30 according to the control of the first processor 11. Additionally, a bus is provided to couple the PCI bridge 14 to the first processor 11 and the first main memory 12.
The second board 20 has the same construction as that of the first board 10. Specifically, the second board 20 includes a second processor 21 for outputting data and a control signal and a second main memory 22 for storing the data according to the control signal. The second board 20 also includes a second PCI bridge 24 for exchanging information with the second board 20 through the PCI bus 30 according to the control of the second processor 21. Additionally, a bus is provided to couple the PCI bridge 24 to the second processor 21 and the second main memory 22.
Because the dual apparatus using the PCI bridge is implemented by the warm standby dual method, the first main memory 12 of the first board 10 and the second main memory 22 of the second board 20 have to be synchronized with each other.
A method for synchronizing memory data of the dual apparatus using the PCI bridge will next be described. It is assumed that the first board 10 is operated as active and the second board 20 is operated as standby.
When there is a need to change data, synchronization of data in the first main memory 12 (with the exception of content in an operating system code region and a stack region) is required. Thus, the first processor 11 of the first board 10 gains access to the first main memory 12 and changes content therein. Afterward, it performs a procedure for changing content in the second main memory 22.
As described above, the first processor 11 sequentially performs the memory content change operation of the first board 10 and the memory content change operation of the second board 20. Accordingly, the first main memory 12 and the second main memory 22 are synchronized with each other.
The operation for changing the memory content will be descried in more detail.
FIG. 2 illustrates a path when the first processor 11 of the first board 10 in the active state changes content of the first main memory 12. For example, when there is data to be written in the first main memory 12, the first processor 11 carries the data and an address (processor bus address) of the first main memory 12 corresponding to the data to the first processor bus 13. Then, the first main memory 12 receives the data and the address through the first processor bus 13 and writes the data in the corresponding address.
When the first processor 11 finishes changing the memory content of the first memory 12, the first processor 11 changes content of the second main memory 22.
FIG. 3 illustrates a path when the first processor 11 of the first board 10 in the active state changes content of the second main memory 22.
The active first processor 11 carries the same data and PCI address as the data that was written in the first main memory 12 to the first processor bus 13. The PCI address corresponds to the processor bus address (address of the first main memory 12). The first PCI bridge 14 then receives the PCI address and the data of the first processor bus 13 and transmits the PCI address and the data to the second PCI bridge 24 of the second board 20 through the PCI bus 30.
The second PCI bridge 24 converts the received PCI address into a processor bus address and carries the converted processor bus address and the data to the second processor bus 23.
The second main memory 22 receives the processor bus address and the data through the second processor bus 23 and writes the data in the corresponding processor bus address of the second main memory 20.
The related art dual apparatus using the PCI bridge has various problems. For example, because the active board processor sequentially writes the same data in the first memory and then in the second memory, resources of the processor of the active board are required for data synchronization between the two memories. Accordingly, data synchronization may consume much time and waste resources of the first processor. In addition, the performance of the first processor may be lowered.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.